1. Field of the Invention
The invention relates to a method of and resulting semiconductor formed by selectively etching an organosilicate glass.
2. Description of the Related Art
Integrated circuits and other semi-conductor based devices often include dielectric layers, which have typically been formed from silicon dioxide, SiO2, to insulate conductive lines on various layers of a semiconductor structure.
To facilitate understanding, FIG. 1A is a schematic cut away view of a substrate 104. A dielectric layer 105, such as silicon oxide SiO2, with metal contacts 106 is placed over the substrate 104. An etch stop layer 108, such as silicon nitride, is place over the dielectric layer 105 and metal contacts 106. A second SiO2 dielectric layer 110 is placed over the etch stop layer 108. A via pattern photoresist mask 112 is placed over the second dielectric layer 110. Vias 114, 116 may be etched into the second dielectric layer 110 according to the pattern of the photoresist mask. It is desirable that all of the vias be etched to the etch stop layer 108, but not through the etch stop layer. Due to various factors such as via size and via location, vias may have different etch rates. In this example, the second via 116 has etched completely through the etch stop layer 108 before the first via 114 is completed. In this example, there is not sufficient selectivity between the dielectric 110 and the stop etch layer 108. In addition, there is not sufficient selectivity between the dielectric 110 and the etch mask 112, so that part of the etch mask is etched through causing a slight etch 120. In addition, in this example, the first via 114 has an undesirable uneven etch front, instead of a flat profile.
The via pattern photoresist mask may then be removed and replaced with a trench pattern photoresist mask 124, as shown in FIG. 1B. A first trench 128 and a second trench 130 are etched through the trench pattern photoresist 124. Since a metal contact 106 is exposed through the second via 116, the etching of the trenches may cause the metal contact 106 to have some corrosion 134.
The trench pattern photoresist may then be removed. An etch stop etch may be used to remove the etch stop layer in the vias, as shown in FIG. 1C. Such an etch stop etch would preferably be selective to etch the etch stop with respect to the dielectric. The trenches and vias may then be filled with metal, which is polished down to form dual damascene structures 136.
To make semiconductor circuits faster they are made more compact with increased operating frequencies, where the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, k, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.2. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO2 may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO2, which materials are suitable for use in forming the dielectric layers in integrated circuits and other semiconductor based devices. To date, a number of promising materials, which are sometimes referred to as “low-k materials”, have been developed. Many of these new dielectrics are organic compounds. For the purposes of this specification, “low-k” will be considered to mean a dielectric constant of lower than about 4.0.
One promising class of organic low-k materials is organosilicate glasses (OSG). By way of example, but not limitation, such organosilicate dielectrics include CORAL™ from Novellus Systems, Inc. of San Jose, Calif.; Black Diamond™ from Applied Materials of Santa Clara, Calif.; AURORA™ from ASM International N.V. and Sumika Film® (spin-on-glass) available from Sumitomo Chemical America, Inc., Santa Clara, Calif.
During semiconductor wafer processing, features of the semiconductor device have been defined in the wafer using well-known patterning and etching processes. In these processes a photoresist material may be deposited on the wafer and may then be exposed to light filtered by a reticle. The reticle may be a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
The development of an effective etching process for an organosilicate glass low-k film such as CORAL™ often takes into account several criteria including etch rate, profile control, selectivity to underlying materials as well as critical dimension (CD) control. The etching of low-k dielectric materials has been approached as if a silicon-based dielectric were being etched. This has not proven particularly effective, as with organic low-k films the chemistries and processes needed to effectively etch the material are substantially different than those for traditional silicon oxide etching.